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ADDRESSING SYSTEM-LEVEL NOISE (SLN) IN DIGITAL AND MIXED-SIGNAL HIGH-END SoCs

What are the Challenges of the new high-end electronic systems ?

Assembling next generation of smartphones, tablets, game consoles as well as devices demanding a high reliability (medical and automation fields for example) today faces critical challenges relating to system level noise propagation.

These challenges increase as SoC integrators wish to put more circuitry on each piece of silicium while lowering power consumption. At the same time, package and PCB designers are pressured by economic constraints.

SoC integration

Putting together complex systems is a challenging task for botth designers and system integrators. CWS unique systemic and hierarchical solution provides each design group with a dedicated toolset. Thus, CWS software products allow analog/RF/Custom IP designers to deliver more robust and tested IPs, digital designers generate black-boxes and noise models ahead of time, allowing SoC integrators or chip architect to evaluate and control noise issues early at the floorplanning stage.

In the unfortunate event that failure is detected on silicon, WaveIntegrityâ„¢ will also provide an extremely effective way to quickly identify a cause and to find the lowest cost design fix.

Below is a non comprehensive list of challenges for which our customers have benefited from the assistance provided by our software:

  • How to increase the number of very high frequency PLLs?
  • How to increase operating frequencies with new I/Os IP (DDR, USBS, etc...)?
  • How to decrease the number of I/O and Power PADs to fit into cheap packages?
  • How to implement robust methodology for integration of high-end Analog/RF/mixed custom IPs in complex SoCs?
  • How to maintain robust SoC with low cost and noisy PCBs?
  • How to fit SoC into stringent noise level guidelines?
  • How to optimize IC cost by merging RF Front end with Back end ICs?
  • How to understand substrate, interconnect , package and PCB noise issues inside SoCs?
  • How to do Full chip Noise Analysis of a big Mix-signal SoC?
  • How to get noise under control early on (before layout completion)
  • How to do quick failure analysis of older designs to better understand reasons of noise issues?
  • How to safely merge several chips into one single SoC?

Package and PCB design

Lowering the cost of consumer electronic systems is likely to cause dramatic noise failures. The impact of selecting cheaper discrete components (such as filters, regulators ...) or decreasing the layer number can be analyse with CWS software.

CWS software products, and NoisePrototyperâ„¢ option in particular, help package and PCB designers to make the best economic decision much before the final die exists on silicon.

Below is a non comprehensive list of challenges for which our customers have benefited from the assistance provided by our software:

  • How to get noise under control early on (before layout completion)?
  • How to do quick failure analysis of older designs to better understand reasons of noise issues?
  • What is the noise impact between bonded and flip-chip packages?
  • Is it safe to merge supplies at package level?
  • What is the impact of PCB trace parasitic?
  • What is the impact of filter choice?
  • Is package and/or PCB decoupling efficient enough?