Solution

HELPING SILICON FOUNDRIES AND RF DESIGN COMMUNITY WITH ACCURATE MODELING OF SILICON SUBSTRATE PARASITICS

What are the Challenges of the new high-end electronic systems ?

The evolution of RF design specifications for IoT, 5G or mmW applications is causing headache to engineers without a perfect correlation between simulations and silicon measurements.

The development of RF front-end modules (FEM) like low-noise amplifiers (LNAs), power amplifiers (PaS) or RF switches would require many silicon iterations without a perfect match.

RF design challenges

A strong expertise is required to design FEM that will meet the specifications required for uplink carrier aggregation. Even with the best expertise, several design iterations will be necessary to achieve the desired linearity while minimizing insertion loss and maximazing power efficiency and battery life.

CWS partners with leading edge silicon foundries with RF PDKs to offer a seamless solution that adds silicon substrate parasitic extraction with silicon-proven accuracy.

Below is a non comprehensive list of benefits acknowledged by current users :

  • Modeling and simulation of full-chip SP9T in 30'
  • Second and third harmonic simulation output within 3dB of silicon measurement
  • 25 % reduction of total chip area
  • >15 dB gain on second harmonic